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1. general description the gtl2007 is a customized translator between dual xeon processors, platform health management, south bridge and power supply lvttl and gtl signals. the gtl2007 is derived from the gtl2006 with an enable function added that disables the error output to the monitoring agent for platforms that monitor the individual error conditions from each processor. this enable function can be used so that false error conditions are not passed to the monitoring agent when the system is unexpectedly powered down. this unexpected power-down could be from a power supply overload, a cpu thermal trip, or some other event of which the monitoring agent is unaware. a typical implementation would be to connect each enable line to the system power good signal or the individual enables to the vrd power good for each processor. typically xeon processors specify a v tt of 1.1 v to 1.2 v, as well as a nominal v ref of 0.73 v to 0.76 v. to allow for future voltage level changes that may extend v ref to 0.63 of v tt (minimum of 0.693 v with v tt of 1.1 v) the gtl2007 allows a minimum v ref of 0.66 v. characterization results show that there is little dc or ac performance variation between these v ref levels. 2. features n operates as a gtl to lvttl sampling receiver or lvttl to gtl driver n operates at gtl - /gtl/gtl+ signal levels n en1 and en2 disable error output n 3.0 v to 3.6 v operation n lvttl i/o not 5 v tolerant n series termination on the lvttl outputs of 30 w n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 500 ma n package offered: tssop28 gtl2007 12-bit gtl to lvttl translator with power good control rev. 02 16 february 2007 product data sheet
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 2 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 3. quick reference data 4. ordering information table 1. quick reference data t amb =25 c. symbol parameter conditions min typ max unit c io input/output capacitance a port; v o = 3.0 v or 0 v - 2.5 3.5 pf b port; v o =v tt or 0 v - 1.5 2.5 pf v ref = 0.73 v; v tt = 1.1 v t plh low-to-high propagation delay na to nb; see figure 4 14 8ns nbi to nao; see figure 5 2 5.5 10 ns t phl high-to-low propagation delay na to nb; see figure 4 2 5.5 10 ns nbi to nao; see figure 5 2 5.5 10 ns v ref = 0.76 v; v tt = 1.2 v t plh low-to-high propagation delay na to nb; see figure 4 14 8ns nbi to nao; see figure 5 2 5.5 10 ns t phl high-to-low propagation delay na to nb; see figure 4 2 5.5 10 ns nbi to nao; see figure 5 2 5.5 10 ns table 2. ordering information t amb = - 40 c to +85 c. type number topside mark package name description version GTL2007PW gtl2007 tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 3 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 5. functional diagram (1) the enable on 7bo1/7bo2 include a delay that prevents the transient condition where 5bi/6bi go from low to high, and the low to high on 5a/6a lags up to 100 ns from causing a low glitch on the 7bo1/7bo2 outputs. fig 1. logic diagram of gtl2007 002aab210 gtl2007 1bi 2bi 27 26 gtl inputs 7bo1 25 7bo2 24 gtl outputs en2 23 lvttl input 11bo 22 gtl output delay (1) 5bi 6bi 21 20 3bi 19 4bi 18 delay (1) gtl inputs 7 11bi 8 11a 9 9bi lvttl input/output (open-drain) gtl input gtl input 1 vref 2 1ao 3 2ao 4 5a 5 6a 6 en1 lvttl input gtl lvttl inputs/outputs (open-drain) lvttl outputs 10 3ao 11 4ao lvttl outputs 10bo1 17 10bo2 16 gtl outputs 12 10ai1 13 10ai2 lvttl inputs 9ao 15 lvttl output 1 1 1 & &
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 4 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin con?guration for tssop28 GTL2007PW vref v cc 1ao 1bi 2ao 2bi 5a 7bo1 6a 7bo2 en1 en2 11bi 11bo 11a 5bi 9bi 6bi 3ao 3bi 4ao 4bi 10ai1 10bo1 10ai2 10bo2 gnd 9ao 002aab209 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 table 3. pin description symbol pin description vref 1 gtl reference voltage 1ao 2 data output (lvttl) 2ao 3 data output (lvttl) 5a 4 data input/output (lvttl), open-drain 6a 5 data input/output (lvttl), open-drain en1 6 enable input (lvttl) 11bi 7 data input (gtl) 11a 8 data input/output (lvttl), open-drain 9bi 9 data input (gtl) 3ao 10 data output (lvttl) 4ao 11 data output (lvttl) 10ai1 12 data input (lvttl) 10ai2 13 data input (lvttl) gnd 14 ground (0 v) 9ao 15 data output (lvttl) 10bo2 16 data output (gtl) 10bo1 17 data output (gtl) 4bi 18 data input (gtl) 3bi 19 data input (gtl)
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 5 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 7. functional description refer to figure 1 logic diag r am of gtl2007 . 7.1 function tables [1] 1ao, 2ao, 3ao, 4ao and 5a/6a condition changed by enn power good signal as described in t ab le 5 and t ab le 6 . 6bi 20 data input (gtl) 5bi 21 data input (gtl) 11bo 22 data output (gtl) en2 23 enable input (lvttl) 7bo2 24 data output (gtl) 7bo1 25 data output (gtl) 2bi 26 data input (gtl) 1bi 27 data input (gtl) v cc 28 positive supply voltage table 3. pin description continued symbol pin description table 4. gtl input signals h = high voltage level; l = low voltage level. input output [1] 1bi/2bi/3bi/4bi/9bi 1ao/2ao/3ao/4ao/9ao ll hh table 5. en1 power good signal h = high voltage level; l = low voltage level. en1 1ao and 2ao 5a l h 5bi disconnected h follows bi 5bi connected table 6. en2 power good signal h = high voltage level; l = low voltage level. en2 3ao and 4ao 6a l h 6bi disconnected h follows bi 6bi connected
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 6 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control [1] the enable on 7bo1/7bo2 includes a delay that prevents the transient condition where 5bi/6bi go from low to high, and the low to high on 5a/6a lags up to 100 ns from causing a low glitch on the 7bo1/7bo2 outputs. [2] open-drain input/output terminal is driven to logic low state by other driver. [1] open-drain input/output terminal is driven to logic low state by other driver. table 7. smi signals h = high voltage level; l = low voltage level. input input output 10ai1/10ai2 9bi 10bo1/10bo2 lll lhl hl l hhh table 8. prochot signals h = high voltage level; l = low voltage level. input input/output output 5bi/6bi 5a/6a (open-drain) 7bo1/7bo2 llh [1] hl [2] l hhh table 9. nmi signals h = high voltage level; l = low voltage level. input input/output output 11bi 11a (open-drain) 11bo lhl ll [1] h hl h
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 7 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 8. application design-in information fig 3. typical application thrmtrip l cpu1 ierr_l forcepr_l cpu2 disable_l gtl2007 prochot l forcepr_l prochot l thrmtrip l ierr_l cpu1 disable_l cpu2 nmi nmi 10bo2 10bo1 4bi 3bi 6bi 5bi en2 7bo2 7bo1 2bi 1bi 1ao 2ao 5a 6a 11a 3ao 4ao 10ai1 10ai2 en1 gnd 9bi 9ao platform health management cpu1 1err_l cpu1 thrmtrip l cpu1 prochot l cpu2 prochot l nmi_l cpu2 1err_l cpu2 thrmtrip l cpu1 smi l cpu2 smi l smi_buff_l southbridge nmi southbridge smi_l power supply power good 1.5 k w to 1.2 k w v cc v tt 56 w 1.5 k w r 2r vref 11b1 v cc v cc 11b0 002aab211 56 w v tt
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 8 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 9. limiting values [1] stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under section 10 recommended oper ating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [3] current into any output in the low state. [4] current into any output in the high state. [5] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 10. recommended operating conditions table 10. limiting values in accordance with the absolute maximum rating system (iec 60134). [1] voltages are referenced to gnd (groun d=0v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v i ik input clamping current v i <0v - - 50 ma v i input voltage a port (lvttl) [2] - 0.5 +4.6 v b port (gtl) [2] - 0.5 +4.6 v i ok output clamping current v o <0v - - 50 ma v o output voltage output in off or high state; a port [2] - 0.5 +4.6 v output in off or high state; b port [2] - 0.5 +4.6 v i ol low-level output current [3] a port - 32 ma b port - 30 ma i oh high-level output current [4] a port - - 32 ma t stg storage temperature - 60 +150 c t j(max) maximum junction temperature [5] - +125 c table 11. operating conditions symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v v tt termination voltage gtl - 1.2 - v v ref reference voltage gtl 0.64 0.8 1.1 v v i input voltage a port 0 3.3 3.6 v b port 0 v tt 3.6 v v ih high-level input voltage a port and enn 2 - - v b port v ref + 0.050 - - v v il low-level input voltage a port and enn - - 0.8 v b port - - v ref - 0.050 v i oh high-level output current a port - - - 16 ma i ol low-level output current a port - - 16 ma b port - - 15 ma t amb ambient temperature operating in free-air - 40 - +85 c
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 9 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 11. static characteristics [1] all typical values are measured at v cc = 3.3 v and t amb =25 c. [2] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [3] this is the increase in supply current for each input that is at the speci?ed lvttl voltage level rather than v cc or gnd. table 12. static characteristics recommended operating conditions; voltages are referenced to gnd (ground = 0 v). t amb = - 40 c to +85 c. symbol parameter conditions min typ [1] max unit v oh high-level output voltage a port; v cc = 3.0 v to 3.6 v; i oh = - 100 m a [2] v cc - 0.2 3.0 - v a port; v cc = 3.0 v; i oh = - 16 ma [2] 2.1 2.3 - v v ol low-level output voltage a port; v cc = 3.0 v; i ol =4ma [2] - 0.15 0.4 v a port; v cc = 3.0 v; i ol =8ma [2] - 0.3 0.55 v a port; v cc = 3.0 v; i ol =16ma [2] - 0.6 0.8 v b port; v cc = 3.0 v; i ol =15ma [2] - 0.13 0.4 v i i input current a port; v cc = 3.6 v; v i =v cc -- 1 m a a port; v cc = 3.6 v; v i =0v - - 1 m a b port; v cc = 3.6 v; v i =v tt or gnd - - 1 m a i cc supply current a or b port; v cc = 3.6 v; v i =v cc or gnd; i o =0ma - 8 12 ma d i cc [3] additional supply current per input; a port or control inputs; v cc = 3.6 v; v i =v cc - 0.6 v - - 500 m a c io input/output capacitance a port; v o = 3.0 v or 0 v - 2.5 3.5 pf b port; v o =v tt or 0 v - 1.5 2.5 pf
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 10 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 12. dynamic characteristics table 13. dynamic characteristics v cc = 3.3 v 0.3 v. symbol parameter conditions min typ [1] max unit v ref = 0.73 v; v tt = 1.1 v t plh low-to-high propagation delay na to nb; see figure 4 148ns nbi to nao; see figure 5 2 5.5 10 ns 9bi to 10bon 2 6 11 ns 11bi to 11bo 2 8 13 ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 4712ns en1 to nao or en2 to nao; see figure 8 2 6.5 10 ns t phl high-to-low propagation delay na to nb; see figure 4 2 5.5 10 ns nbi to nao; see figure 5 2 5.5 10 ns 9bi to 10bon 2 6 11 ns 11bi to 11bo [2] 21421ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 100 205 350 ns en1 to nao or en2 to nao; see figure 8 2 6.5 10 ns t plz low to off-state propagation delay nbi to na (i/o); see figure 6 21318ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 9 137ns t pzl off-state to low propagation delay nbi to na (i/o); see figure 6 21216ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 9 2710ns
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 11 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control [1] all typical values are at v cc = 3.3 v and t amb =25 c. [2] includes ~7.6 ns rc rise time of test load pull-up on 11a, 1.5 k w pull-up and 21 pf load on 11a has about 23 ns rc rise time. 12.1 waveforms v m = 1.5 v at v cc 3 3.0 v for a ports; v m =v ref for b ports. v ref = 0.76 v; v tt = 1.2 v t plh low-to-high propagation delay na to nb; see figure 4 148ns nbi to nao; see figure 5 2 5.5 10 ns 9bi to 10bon 2 6 11 ns 11bi to 11bo 2 8 13 ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 4712ns en1 to nao or en2 to nao; see figure 8 2 6.5 10 ns t phl high-to-low propagation delay na to nb; see figure 4 2 5.5 10 ns nbi to nao; see figure 5 2 5.5 10 ns 9bi to 10bon 2 6 11 ns 11bi to 11bo [2] 21421ns 5bi to 7bo1 or 6bi to 7bo2; see figure 7 100 205 350 ns en1 to nao or en2 to nao; see figure 8 2 6.5 10 ns t plz low to off-state propagation delay nbi to na (i/o); see figure 6 21318ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 9 137ns t pzl off-state to low propagation delay nbi to na (i/o); see figure 6 21216ns en1 to 5a (i/o) or en2 to 6a (i/o); see figure 9 2710ns table 13. dynamic characteristics continued v cc = 3.3 v 0.3 v. symbol parameter conditions min typ [1] max unit v m = 3.0 v for a port and v tt for b port a port to b port a. pulse duration b. propagation delay times fig 4. voltage waveforms 002aaa999 v oh 0 v t p v m v m 002aab000 3.0 v 0 v v tt v ol t plh t phl v ref v ref 1.5 v 1.5 v input output
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 12 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control prr 10 mhz; z o =50 w ; t r 2.5 ns; t f 2.5 ns fig 5. propagation delay, nbi to nao fig 6. nbi to na (i/o) fig 7. 5bi to 7bo1 or 6bi to 7bo2 fig 8. en1 to nao or en2 to nao fig 9. en1 to 5a (i/o) or en2 to 6a (i/o) 002aab001 v tt 1 / 3 v tt v oh v ol t plh t phl 1.5 v 1.5 v v ref v ref input output 002aab002 v tt 1 / 3 v tt v cc t plz t pzl v ref v ref input output v ol + 0.3 v 1.5 v 002aab003 v tt 1 / 3 v tt v tt v ol t plh t phl v ref v ref input output v ref v ref 002aab004 3.0 v 0 v v oh v ol t plh t phl 1.5 v 1.5 v input output 1.5 v 1.5 v 002aab005 3.0 v 0 v v oh v ol t plz t pzl 1.5 v 1.5 v input output 1.5 v v ol + 0.3 v
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 13 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 13. test information fig 10. load circuit for a outputs fig 11. load circuit for b outputs r l = load resistor. c l = load capacitance; includes jig and probe capacitance. r t = termination resistance; should be equal to z o of pulse generators. fig 12. load circuit for open-drain lvttl i/o pulse generator v o c l 50 pf 002aab006 r l 500 w r t v i v cc dut pulse generator dut v o c l 30 pf 50 w 002aab264 r t v i v cc v tt pulse generator dut v o c l 21 pf r l 1.5 k w 002aab265 r t v i v cc v cc
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 14 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 14. package outline fig 13. package outline sot361-1 (tssop28) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 114 28 15 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 a max. 1.1
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 15 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 15. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 15.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 15.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 16 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 15.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 14 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 14 and 15 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 14 . table 14. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 15. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 17 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 16. abbreviations msl: moisture sensitivity level fig 14. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 16. abbreviations acronym description cdm charged device model cmos complementary metal oxide silicon cpu central processing unit dut device under test esd electrostatic discharge gtl gunning transceiver logic hbm human body model lvttl low voltage transistor-transistor logic mm machine model prr pulse rate repetition ttl transistor-transistor logic vrd voltage regulator down
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 18 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 17. revision history table 17. revision history document id release date data sheet status change notice supersedes gtl2007_2 20070216 product data sheet - gtl2007_1 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? data sheet descriptive title changed from 13-bit gtl to lvttl translator with power good control to 12-bit gtl to lvttl translator with power good control ? section 1 gener al descr iption : C 4 th paragraph re-written C deleted (old) 5 th paragraph ? section 2 f eatures : added (new) 2 nd bullet item ? figure 1 logic diag r am of gtl2007 : updated symbols to iec convention ? figure 3 t ypical application modi?ed: C in blocks cpu1 and cpu2, changed smi l to disable_l C in block platform health management: changed cpu2 ierr_l to cpu2 1err_l ? t ab le 10 limiting v alues : parameter de?nitions updated; added t ab le note 3 and t ab le note 4 ? t ab le 13 dynamic char acter istics : data reorganized (no speci?cation changed) ? t ab le 16 ab bre viations : added dut gtl2007_1 (9397 750 13264) 20050602 product data sheet - -
gtl2007_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 16 february 2007 19 of 20 nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 18.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 18.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 19. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors gtl2007 12-bit gtl to lvttl translator with power good control ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 16 february 2007 document identifier: gtl2007_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 function tables . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 application design-in information . . . . . . . . . . 7 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 recommended operating conditions. . . . . . . . 8 11 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 12 dynamic characteristics . . . . . . . . . . . . . . . . . 10 12.1 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 test information . . . . . . . . . . . . . . . . . . . . . . . . 13 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 15 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15.1 introduction to soldering . . . . . . . . . . . . . . . . . 15 15.2 wave and re?ow soldering . . . . . . . . . . . . . . . 15 15.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 15.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 16 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 18.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 contact information. . . . . . . . . . . . . . . . . . . . . 19 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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